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k4x56163pe-l(f)g march 2004 1 mobile-ddr sdram 16m x16 mobile ddr sdram features ? 1.8v power supply, 1.8v i/o power ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? four banks operation ? differential clock inputs(ck and ck ) ? mrs cycle with address key programs - cas latency ( 3 ) - burst length ( 2, 4, 8 ) - burst type (sequential & interleave) - partial self refresh type ( full, 1/2, 1/4 array ) - internal temperature compensated self refresh - driver strengt h ( 1, 1/2, 1/4, 1/8 ) ? all inputs except data & dm are sampled at the positive going edge of the system clock(ck). ? data i/o transactions on both edges of data strobe, dm for masking. ? edge aligned data output, center aligned data input. ? no dll; ck to dqs is not synchronized. ? ldm/udm for write masking only. ? 7.8us auto refresh duty cycle. ? csp package. operating frequency *cl : cas latency ddr200 ddr133 speed @cl3 100mhz 66mhz column address configuration dm is internally loaded to match dq and dqs identically. organization row address column address 16mx16 a0 ~ a12 a0-a8
k4x56163pe-l(f)g march 2004 2 mobile-ddr sdram package dimension and pin configuration ball name ball function ck, ck system differential clock cs chip select cke clock enable a0 ~ a12 address ba0 ~ ba1 bank select address ras row address strobe cas column address strobe we write enable l(u)dm data input mask l(u)dqs data strobe dq0 ~ 15 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground < bottom view *1 > 60ball(6x10) csp 1 2 3 7 8 9 av ss dq15 v ssq v ddq dq0 v dd bv ddq dq13 dq14 dq1 dq2 v ssq cv ssq dq11 dq12 dq3 dq4 v ddq dv ddq dq9dq10dq5 dq6 v ssq ev ssq udqs dq8 dq7 ldqs v ddq fv ss udm n.c. n.c. ldm v dd gckeckck we cas ras ha9a11a12cs ba0 ba1 j a6 a7 a8 a10/ap a0 a1 kv ss a4 a5 a2 a3 v dd < top view *2 > k4x56163pe-xxxx samsung wee k #a1 ball origin indicator < top view *2 > *2: top view a a1 z j b encapsulant max. 0.20 *1: bottom view symbol min typ max a 0.90 0.95 1.00 a 1 0.30 0.35 0.40 e-11.0- e 1 -6.4- d-9.0- d 1 -7.2- e - 0.80 - jb 0.40 0.45 0.50 z--0.10 [unit:mm] e 1 521 63 4 8 97 f e d c b j h g a e d d/2 e e/2 d 1 k
k4x56163pe-l(f)g march 2004 3 mobile-ddr sdram input/output function description symbol type description ck, ck input clock : ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . internal clock signals are derived from ck/ck . cke input clock enable : cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke , are disabled during power-down and self refresh mode which are contrived for low standby power consumption. cs input chip select : cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. *1 ldm,udm input input data mask : dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0-dq7 ; udm corresponds to the data on dq8-dq15. ba0, ba1 input bank address inputs : ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. a [n : 0] input address inputs : provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. ba0 and ba1 determines which mode register ( mode register or extended mode register ) is loaded during the mode register set command. *1 dq i/o data input/output : data bus *1 ldqs,udqs i/o data strobe : output with read data, input with write data. edge-aligned with read data, centered in write data. it is used to fetch write data. for the x1 6, ldqs corresponds to the data on dq0-dq7 ; udqs corresponds to the data on dq8-dq15. nc - no connect : no internal electrical connection is present. vddq supply dq power supply : 1.7v to 1.95v. vssq supply dq ground. vdd supply power supply : 1.7v to 1.95v.. vss supply ground.
k4x56163pe-l(f)g march 2004 4 mobile-ddr sdram functional description simplified state diagram figure.1 state diagram read self refresh auto refresh power down row active reada writea writea pre charge power on idle mode power down register set refs refsx refa mrs ckel ckeh act ckeh ckel write write writea pre power applied reada pre pre reada reada read read automatic sequence command sequence writea burst stop mode register set extended emrs self refresh partial pre
k4x56163pe-l(f)g march 2004 5 mobile-ddr sdram note: 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. 6. issue a extended mode register set command to define pasr or ds operating type of the device after normal mrs. emrs cycle is not mandatory and the emrs command needs to be issued only when either pasr or ds is used. the default state without emrs command issued is half driver strength, and full array refreshed . the device is now ready for the operation selected by emrs. for operating with pasr or ds, set pasr or ds mode in emrs setting stage. in order to adjust another mode in the state of pasr or ds mode, additional emrs set is required but power up sequence is not n eeded again at this time. in that case, all banks have to be in idle state prior to adjusting emrs set. 0123456789101112131415 high level is necessary cke cs ras cas addr ba0 ba1 dq a10/ap we ck ck power up sequence for mobile ddr sdram dqm precharge t rp 16 17 18 19 20 key raa raa hi-z hi-z t arfc t arfc (all bank) auto refresh auto refresh normal mrs extended mrs row active (a-bank) : don?t care key hi
k4x56163pe-l(f)g march 2004 6 mobile-ddr sdram mode register definition mode register set(mrs) figure.2 mode register set the mode register is designed to support the variou s operating modes of ddr sdram. it includes cas latency, addressing mode, burst length, test mode and vendor specific options to make d dr sdram useful for variety of a pplications. the default value of the mode register is not defined, t herefore the mode register must be written in the power up sequenc e of ddr sdram. the mode reg- ister is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already high prior to writing into the mode register). th e state of address pins a0 ~ a11 and ba0, ba1 in the same cycle as cs , ras , cas and we going low is written in the mode register. two clock cycles are required to complete the writ e operation in the mode register. even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be change d with the same command and four clock cycles. this command must be issued only when all banks are in the idle state. if mode reg - ister is changed, extended mode register automatically is reset and come into default state. so extended mode register must be set again. the mode register is divided into various fields depending on functionality. the burst length uses a0 ~ a2, addressing m ode uses a3, cas latency(read latency from column address) uses a4 ~ a6. a7 is used for test mode. ba0 and ba1 must be set to low for normal ddr sdram operation. figure.2 mode register set burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve a 3 burst type 0 sequential 1 interleave mode register 0 bt burst length 0 0 0 0 0 0 cas latency a 6 a 5 a 4 cas latency 000 reserve 001 reserve 010 reserve 011 3 100 reserve 101 reserve 110 reserve 111 reserve address bus ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a12 0
k4x56163pe-l(f)g march 2004 7 mobile-ddr sdram burst address ordering for burst length burst length starting address(a2, a1, a0) sequential mode interleave mode 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
k4x56163pe-l(f)g march 2004 8 mobile-ddr sdram extended mode register set(emrs) the extended mode register is designed to support partial array se lf refresh or driver strength. emrs cycle is not mandatory a nd the emrs command needs to be issued only when either pasr or ds is used. the default state wit hout emrs command issued is +85 c, all 4 banks refreshed and the half size of driver strength . the extended mode register is written by asserting low on cs , ras , cas , we and high on ba1 ,low on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). t he state of address pins a0 ~ a11 in the same cycle as cs , ras , cas and we going low is written in the extended mode register. two clock cycles are required to co mplete the write operation in the extended mode register. even if the power-up sequence is finished and some read or write operations is executed afterward, the m ode register contents can be chang ed with the same command and four clock cycles. but this command must be issued only when all banks are in the idle state. a0 - a2 are used for partial array self refresh and a5 - a6 are used for driver strength. "high" on ba1 and"low" on ba0 are used for emrs. all the other address pins except a0,a1,a2, ba1, ba0 must be set to low for proper emrs operation. refer to the table for spec ific codes. extended mrs for pasr(partial array self refresh) & tcsr(internal temperature compensated self refresh) ds a 6 a 5 driver strength 0 0 full 0 1 1/2 1 0 1/4 1 1 1/8 address bus ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 1 pasr 0 0 0 0 0 pasr a 2 a 1 a 0 # of banks 0 0 0 full array 0 0 1 1/2 array 0 1 0 1/4 array 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved 0 0 internal tcsr self refresh cycle is controlled automatically by internal tem- perature sensor and control cir- cuit according to the two temperature ; max 40 c,max 85 c ds 0 a12 0
k4x56163pe-l(f)g march 2004 9 mobile-ddr sdram figure.3 emrs code and tcsr , pasr note : 1. in order to save power consumption, mobile ddr sdram includes pasr option. 2. mobile ddr sdram supports three kinds of pasr in self refresh mode; full array, 1/2 array, 1/4 array. partial self refresh area partial array self refresh (pasr ) ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 note : 1. in order to save power consumption, mobile ddr sdram includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range ; max. 40 c, max. 85 c. 2. if the emrs for external tcsr is issued by the controller, this emrs code for tcsr is ignored. temperature range self refresh current (icc 6) unit full array 1/2 array 1/4 array max. 40 c 150 125 115 ua max. 85 c 400 300 250 internal temperature compensated self refresh (tcsr) - full array - 1/2 array - 1/4 array
k4x56163pe-l(f)g march 2004 10 mobile-ddr sdram precharge the precharge command is used to precharge or close a bank that has been activated. the precharge command is issued when cs , ras and we are low and cas is high at the rising edge of th e clock. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank select a ddresses(ba0, ba1) are used to define which bank is precharged when the command is initiated. for write cycle, twr(min.) must be satisfied until the precharge command can be issued. after trp f rom the precharge, an active command to the same bank can be initiated. bank selection for precharge by bank address bits a10/ap ba1 ba0 precharge 000 bank a only 001 bank b only 0 1 0 bank c only 0 1 1 bank d only 1 x x all banks no operation(nop) & device deselect the device should be deselected by deactivating the cs signal. in this mode ddr sdram should ignore all the control inputs. the ddr sdrams are put in nop mode when cs is active and by deactivating ras , cas and we . both device deselect and nop com- mand can not affect operation already in progress. so even if t he device is deselected or nop command is issued under operation , operation will be complete.
k4x56163pe-l(f)g march 2004 11 mobile-ddr sdram row active the bank activation command is issued by holding cas and we high with cs and ras low at the rising edge of the clock(ck). the ddr sdram has four independent banks, so two bank select addresses(ba0, ba1) are required. the bank activation command must be applied before any read or write operation is executed. the delay from the bank activation command to the first read or write command must meet or exceed the minimum of ras to cas delay time(trcd min). once a bank has been activated, it must be precharged before another bank activation command can be appl ied to the same bank. the minimum time interval between inter- leaved bank activation commands(bank a to bank b and vice versa) is the bank to bank delay time(trrd min). address command ras -cas delay(trcd) bank activation command cycle bank a row addr. bank a col. addr. bank a activate write a with auto nop precharge ras -ras delay time(trrd) bank b row addr. bank a row. addr. bank b activate bank a activate nop row cycle time(trc) tn tn+1 tn+2 2 0 1 : don t care ck ck read bank this command is used after the row activate command to initiate the burst read of data. the read command is initiated by activa ting ras , cs , cas , and deasserting we at the same clock sampling(rising) edge as descr ibed in the command truth table. the length of the burst and the cas latency time will be determined by the values programmed during the mrs cycle. write bank this command is used after the row activate command to initiate the burst write of data. the write command is initiated by acti vating ras , cs , cas , and we at the same clock sampling(rising) edge as described in the command truth table. t he length of the burst will be determined by the values programmed during the mrs cycle. figure.4 bank activation command cycle timing 5 3 4 nop nop nop
k4x56163pe-l(f)g march 2004 12 mobile-ddr sdram burst read operation burst read operation in ddr sdram is in the same manner as t he sdram such that the burst read command is issued by assert- ing cs and cas low while holding ras and we high at the rising edge of the clock(ck) after trcd from the bank activation. the address inputs (a0~a9) determine the starting address for the burst. the mode register sets type of burst(sequential or interle ave) and burst length(2, 4, 8). the first output data is available after the cas latency from the read command, and the consecutive data are presented on the falling and rising edge of data strobe(d qs) adopted by ddr sdram until the burst length is completed. essential functi onality for ddr sdram the essential functionality that is required for t he ddr sdram device is described in this chapter figure.5 burst read operation timing command < burst length=4, cas latency= 3 > read a nop nop nop nop nop nop nop nop 2 01 5 34 8 67 dqs dqs cas latency=3 dout 0 dout 1 dout 2 dout 3 t rpst t rpre preamble postamble ck ck t sac
k4x56163pe-l(f)g march 2004 13 mobile-ddr sdram burst write operation the burst write command is issued by having cs , cas , and we low while holding ras high at the rising edge of the clock(ck). the address inputs determine the starting column address. there is no write latency relative to dqs required for burst write cycle . the first data of a burst write cycle must be applied on the dq pins tds(data-in setup time) prior to data strobe edge enabled afte r tdqss from the rising edge of the clock( ck) that the write command is issued. the remaining data inputs must be supplied on each sub se- quent falling and rising edge of data strobe until the burst lengt h is completed. when the bu rst has been finished, any additi onal data supplied to the dq pins will be ignored. figure.6 burst write operation timing 1. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown (dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. *1 command < burst length=4 > nop writea nop nop nop writeb nop nop nop dqs dqs din 3 din 0 din 1 din 2 t dqssmax 2 01 5 34 8 67 t wpres*1 ck ck din 3 din 0 din 1 din 2 *1
k4x56163pe-l(f)g march 2004 14 mobile-ddr sdram read interrupted by a read a burst read can be interrupted before completion of the burst by new read command of any bank. when the previous burst is interrupted, the remaining addresses are overridden by the new addr ess with the full burst length. the data from the first read com- mand continues to appear on the outputs until the cas latency from the interrupting read command is satisfied. at this point the data from the interrupting read command appears. read to read interval is minimum 1 clock. read interrupted by a write & burst stop to interrupt a burst read with a write command, burst stop comma nd must be asserted to avoid data contention on the i/o bus by placing the dqs(output drivers) in a high impedance state. to insure the dqs are tri-stated one cycle before the beginning of the write operation, burst stop command must be applied at least 2 clock cycles for cl=2 and at least 3 clock cycles for cl=3 befor e the write command. the following functionality establishes how a write command may interrupt a read burst. 1. for write commands interrupting a read burst, a burst terminate command is required to stop the read burst and tristate the dq bus prior to valid input write data. once the burst termi nate command has been issued, the minimum delay to a write command = ru(cl) [cl is the cas latency and ru means round up to the nearest integer]. 2. it is illegal for a write command to interrupt a read with autoprecharge command. figure.7 read interrupted by a read timing figure.8 read interrupted by a write and burst stop timing. command < burst length=4, cas latency=3 > read a read b nop nop nop nop nop nop nop dqs dqs cas latency=3 dout a 0 dout a 1 dout b 0 dout b 1 dout b 2 dout b 3 ck, ck 2 01 5 34 8 67 t rpre preamble command < burst length=4, cas latency=3 > read burst stop nop write nop nop nop dqs dqs cas latency=3 dout 0 dout 1 din 0 din 1 din 2 din 3 ck, ck 2 01 5 34 8 67 nop t wpreh t wpres t rpre preamble t dqss t sac t sac
k4x56163pe-l(f)g march 2004 15 mobile-ddr sdram read interrupted by a precharge a burst read operation can be interrupted by precharge of the same bank. the minimum 1 clock is required for the read to precha rge intervals. a precharge command to output disable latency is equivalent to the cas latency. when a burst read command is issued to a ddr sdram, a prec harge command may be issued to the same bank before the read burst is complete. the following functionality determines when a precharge command may be given during a read burst and when a new bank activate command may be issued to the same bank. 1. for the earliest possible precharge command without interrupt ing a read burst, the precharge command may be given on the rising clock edge which is cl clock cycles before the end of the read burst where cl is the cas latency. a new bank activate command may be issued to the same bank after trp (ras precharge time). 2. when a precharge command interrupts a read burst operation, the precharge command may be given on the rising clock edge which is cl clock cycles before the last data from the interrupted read burst where cl is the cas latency. once the last data word has been output, the output buffers are tristated. a new bank activate command may be issued to the same bank after trp. 3. for a read with autoprecharge command, a new bank activate command may be issued to the same bank after trp where trp begins on the rising clock edge which is cl clock cycles before the end of the read burst where cl is the cas latency. during read with autoprecharge, the initiation of the internal prechar ge occurs at the same time as the earliest possible external precharge command would initiate a precharge operation withou t interrupting the read burst as described in 1 above. 4. for all cases above, trp is an analog delay that needs to be converted into clock cycles. the number of clock cycles between a precharge command and a new bank activate command to the sa me bank equals trp/tck (where tck is the clock cycle time) with the result rounded up to the nearest inte ger number of clock cycles. (note that rounding to x.5 is not possible since the precharge and bank activate commands can only be given on a rising clock edge).in all cases, a precharge operation cannot be initiated unless tras(min) [minimum bank activate to prec harge time] has been satisfied. this includes read with autoprecharge commands where tras(min) must still be satisfied such that a read with autoprecharge command has the same timing as a read command followed by the earliest possi ble precharge command which does not interrupt the burst. figure.9 read interrupted by a precharge timing command < burst length=8, cas latency=3 > read nop precharge nop nop nop nop nop nop dqs dqs cas latency=3 dout 0 dout 1 dout 2 dout 3 interrupted by precharge 2 01 5 34 8 67 dout 4 dout 5 dout 6 dout 7 1tck t rpre ck, ck t sac
k4x56163pe-l(f)g march 2004 16 mobile-ddr sdram write interrupted by a write a burst write can be interrupted before completion of the burst by a new write command, with the only restriction that the inte rval that separates the commands must be at least one clock cycle. wh en the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into th e device until the programmed burst length is satisfied. command < burst length=4 > nop write a write b nop nop nop nop nop nop dqs dqs din a 0 din a 1 din b 0 din b 1 din b 2 din b 3 1tck 2 01 5 34 8 67 ck ck figure.10 write interrupted by a write timing
k4x56163pe-l(f)g march 2004 17 mobile-ddr sdram write interrupted by a precharge & dm a burst write operation can be interrupted before completion of t he burst by a precharge of the same bank. random column access is allowed. a write recovery time(twr) is required from the last data to precharge command. when precharge command is asserted, any residual data from the burst write cycle must be masked by dm. precharge timing for write operations in dr ams requires enough time to allow ??write re covery?? which is the time required by a dram core to properly store a full ??0?? or ??1?? level before a pr echarge operation. for ddr sdram, a timing parameter, twr, is us ed to indicate the required amount of time between the last valid write operation and a precharge command to the same bank. the precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is s ampled by the input clock. inside the sdram, th e data path is eventually synchronized with the address path by switching clock domain s from the data strobe clock domain to the input clock domain. this makes the definition of when a precharge operation can be in itiated after a write very complex since the write recovery parameter mu st reference only the clock domain that is used to time the int ernal write operation, i.e., the input clock domain. twr starts on the rising clock edge after the last possible dqs edge that strobed in the last valid data and ends on the rising clock edge that strobes in the precharge command. 1. for the earliest possible precharge command following a writ e burst without interrupting the burst, the minimum time for w rite recovery is defined by twr. 2. when a precharge command interrupts a write burst operation, the data mask pin, dm, is used to mask input data during the time between the last valid write data and the rising clock edge on which the precharge command is given. during this time, the dqs input is still required to strobe in the state of dm. the minimum time for write recovery is defined by twr. figure.11 write interrupted by a precharge and dm timing dina 2 dina 3 command < burst length=8 > nop write a nop nop precharge nop nop write b dqs dqs dina 0 dina 1 dina 4 dina 5 dinb 0 dinb 1 dina 6 dina 7 twr dqs dqs twr t dqssmin dina 0 dina 1 dina 2 dina 3 dina 4 dina 5 dina 6 dina 7 dm dinb 0 dinb 1 t dqssmax ck, ck 2 01 5 34 8 67 min tdqss max tdqss dm t wpres t wpreh t wpres t wpreh nop t dqssmax t wpres t wpreh t dqssmin t wpres t wpreh dinb 2
k4x56163pe-l(f)g march 2004 18 mobile-ddr sdram 3. for a write with autoprecharge command, a new bank activa te command may be issued to the same bank after twr+trp where twr+trp starts on the falling dqs edge that strobed in the last valid data and ends on the rising clock edge that strobes in th e bank activate command. during write with autoprecharge, the initia tion of the internal precharge occurs at the same time as th e earliest possible external precharge command without interrupting the write burst as described in 1 above. 4. in all cases, a precharge operation cannot be initiated unless tras(min) [minimum bank activate to precharge time] has be en satisfied. this includes write with autoprecharge commands w here tras(min) must still be sa tisfied such that a write with autoprecharge command has the same timing as a write comma nd followed by the earliest possible precharge command which does not interrupt the burst. 5. refer to "3.3.2 burst write operation" burst stop the burst stop command is initiated by having ras and cas high with cs and we low at the rising edge of the clock(ck). the burst stop command has the fewest restrictions maki ng it the easiest method to use when te rminating a burst read operation before it has been completed. when the burst stop command is issued during a burst read cycle, the pair of data and dqs(data strobe) go to a high impedance state after a delay which is equal to the cas latency set in the mode register. the burst stop command, however, is not supported during a write burst operation. the burst stop command is a mandatory feature for ddr sdrams. the following functionality is required: 1. the bst command may only be issued on the rising edge of the input clock, ck. 2. bst is only a valid command during read bursts. 3. bst during a write burst is undefined and shall not be used. 4. bst applies to all burst lengths. 5. bst is an undefined command during read with autoprecharge and shall not be used. 6. when terminating a burst read command, the bst command must be issued l bst (?bst latency?) clock cycles before the clock edge at which the output buffers are tristated, where l bst equals the cas latency for read operations. 7. when the burst terminates, t he dq and dqs pins are tristated. the bst command is not byte controllable and applies to all bits in the dq data word and the(all) dqs pin(s). figure.12 burst stop timing command < burst length=4, cas latency= 3 > read a burst stop nop nop nop nop nop nop nop dqs dqs cas latency=3 dout 0 dout 1 ck, ck 2 01 5 34 8 67 the burst read ends after a delay equal to the cas latency.
k4x56163pe-l(f)g march 2004 19 mobile-ddr sdram dm masking the ddr sdram has a data mask function that can be used in conjunc tion with data write cycle, not read cycle. when the data mas k is activated (dm high) during write operation, ddr sdram does not accept the corresponding data.(dm to data-mask latency is zero). dm must be issued at the rising or falling edge of data strobe. figure.13 dm masking timing command < burst length=8 > write nop nop nop nop nop nop nop nop dqs dqs din 0 din 1 din 2 din 3 dm din 4 din 5 din 6 din7 masked by dm=h ck, ck 2 01 5 34 8 67 t dqssmax t wpres t wpreh
k4x56163pe-l(f)g march 2004 20 mobile-ddr sdram read with auto precharge if a read with auto-precharge command is issued, the ddr sdram automatically enters the precharge operation bl/2 clock later from a read with auto-precharge command when tras(min) is satisfie d. if not, the start point of precharge operation will be de layed until tras(min) is satisfied. once the pr echarge operation has started, the bank cannot be reactivated and the new command can not be asserted until the precharge time(trp) has been satisfied. figure.14 read with auto precharge timing command < burst length=4, cas latency= 3> bank a nop read a nop nop nop nop active auto precharge 2 01 5 34 8 67 dqs dqs cas latency=3 dout0 dout1 dout2 dout3 nop t rp * bank can be reactivated at completion of t rp ck, ck nop nop nop nop 91011 tras(min) auto-precharge starts *1 *note : 1. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge , cas interrupt of the same bank is illegal
k4x56163pe-l(f)g march 2004 21 mobile-ddr sdram write with auto precharge if a10 is high when write command is issued , the write with auto -precharge function is performed. any new command to the same bank should not be issued until the internal precharge is comple ted. the internal precharge begins after keeping twr(min). < burst length=4 > figure 15. write with auto precharge timing command bank a nop write a nop nop nop nop active auto precharge 2 01 5 34 8 67 dqs dqs din 0 din 1 din 2 din 3 nop t rp * bank can be reactivated at completion of t rp ck, ck nop nop nop nop 91011 t wr internal precharge start *1 *note : 1. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge , cas interrupt of the same bank is illegal
k4x56163pe-l(f)g march 2004 22 mobile-ddr sdram auto refresh & self refresh auto refresh command cke pre t rp t arfc(min) auto = high refresh cmd an auto refresh command is issued by having cs , ras and cas held low with cke and we high at the rising edge of the clock(ck). all banks must be precharged and idle for trp(min) before the auto refresh command is applied. no control of the external addre ss pins is required once this cycle has started because of the inte rnal address counter. when the refresh cycle has completed, al l banks will be in the idle state. a delay between the auto refresh command and the next activate command or subsequent auto refresh co m- mand must be greater than or equal to the tarfc(min). ck ck figure.16 auto refresh timing a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. after 1 clock cycle from t he self refresh command, all of the external cont rol signals including system clock(ck, ck ) can be disabled except cke. the clock is inter- nally disabled during self refresh operation to reduce power. to exit the self refresh mode, supply stable clock input before r eturn- ing cke high, assert deselect or nop command and then assert c ke high. in case that the system uses burst auto refresh during normal opreation, it is recommended to use burst 8192 auto re fresh cycle immediately before entering self refresh mode and after exiting in self refresh mode. on the other hand, if t he system uses the distributed auto re fresh, the system only has to keep the refresh duty cycle. self refresh command cke stable clock t is nop self refresh ck, ck t srfx(min) t is figure.17 self refresh timing active
k4x56163pe-l(f)g march 2004 23 mobile-ddr sdram figure.18 power down entry and exit timing cke precharge active power down the device enters power down mode when cke low,and it exits when cke high. once the power down mode is initiated, all of the receiver circuits except ck and cke are gated off to reduce power consumption. the both bank should be in idle state prior to e nter- ing the precharge power down mode and cke should be set high at least 1 tck+tis prior to row active command. during power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period(tref) of the device. power entry down precharge command ck, ck t is t is t is t is 2 01 5 34 8 67 12 10 11 13 9 power exit down precharge power entry down active power exit down active read (nop) t pdex
k4x56163pe-l(f)g march 2004 24 mobile-ddr sdram command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba0,1 a10/ap a11, a9 ~ a0 note register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv lcolumn address (a0~a8) 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv lcolumn address (a0~a8) 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv vv exit l h x x x x precharge power down mode entry h l hx x x x lh hh exit l h hx x x lv vv dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 1. op code : operand code. a0 ~ a11 & ba0 ~ ba1 : program keys. (@emrs/mrs) 2.emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ ba1 : bank select addresses. 5. if a10/ap is "high" at row precharge, ba0 and ba1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram.
k4x56163pe-l(f)g march 2004 25 mobile-ddr sdram functional truth table current state cs ras cas we address command action precharge standby l h h l x burst stop illegal*2 l h l x ba, ca, a10 read/write illegal*2 l l h h ba, ra active bank active, latch ra l l h l ba, a10 pre/prea illegal*4 l l l h x refresh auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 active standby l h h l x burst stop nop l h l h ba, ca, a10 read/reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write/writea begin write, latch ca, determine auto-precharge l l h h ba, ra active bank active/illegal*2 llhl ba, a10 pre/prea precharge/precharge all l l l h x refresh illegal l l l l op-code, mode-add mrs illegal read l h h l x burst stop terminate burst l h l h ba, ca, a10 read/reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a10 write/writea illegal l l h h ba, ra active bank active/illegal*2 l l h l ba, a10 pre/prea terminate burst, precharge l l l h x refresh illegal l l l l op-code, mode-add mrs illegal
k4x56163pe-l(f)g march 2004 26 mobile-ddr sdram functional truth table current state cs ras cas we address command action write l h h l x burst stop illegal l h l h ba, ca, a10 read/reada terminate burst with dm=high, latch ca, begin read, determine auto-precharge*3 l h l l ba, ca, a10 write/writea terminate burst, latch ca, begin new write, determine auto-pre- charge*3 l l h h ba, ra active bank active/illegal*2 l l h l ba, a10 pre/prea terminate burst with dm=high, precharge l l l h x refresh illegal llllop-code, mode-addmrs illegal read with auto precharge *6 (reada) l h h l x burst stop illegal l h l h ba, ca, a10 read/reada *6 l h l l ba, ca, a10 write/writea illegal l l h h ba, ra active *6 llhl ba, a10 pre/prea *6 l l l h x refresh illegal llllop-code, mode-addmrs illegal write with auto recharge *7 (writea) l h h l x burst stop illegal l h l h ba, ca, a10 read/reada *7 l h l l ba, ca, a10 write/writea *7 l l h h ba, ra active *7 l l h l ba, a10 pre/prea *7 l l l h x refresh illegal llllop-code, mode-addmrs illegal
k4x56163pe-l(f)g march 2004 27 mobile-ddr sdram functional truth table current state cs ras cas we address command action precharging (during trp) l h h l x burst stop illegal*2 l h l x ba, ca, a10 read/write illegal*2 l l h h ba, ra active illegal*2 l l h l ba, a10 pre/prea nop*4(idle after trp) l l l h x refresh illegal llllop-code, mode-add mrs illegal row activating (from row active to trcd) l h h l x burst stop illegal*2 l h l x ba, ca, a10 read/write illegal*2 l l h h ba, ra active illegal*2 llhl ba, a10 pre/prea illegal*2 l l l h x refresh illegal llllop-code, mode-add mrs illegal write recovering (during twr or tcdlr) l h h l x burst stop illegal*2 l h l h ba, ca, a10 read illegal*2 l h l l ba, ca, a10 write write l l h h ba, ra active illegal*2 l l h l ba, a10 pre/prea illegal*2 l l l h x refresh illegal llllop-code, mode-add mrs illegal
k4x56163pe-l(f)g march 2004 28 mobile-ddr sdram functional truth table current state cs ras cas we address command action re- freshing l h h l x burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal l l h l ba, a10 pre/prea illegal l l l h x refresh illegal l l l l op-code, mode-add mrs illegal mode register setting l h h l x burst stop illegal l h l x ba, ca, a10 read/write illegal l l h h ba, ra active illegal llhl ba, a10 pre/prea illegal l l l h x refresh illegal l l l l op-code, mode-add mrs illegal
k4x56163pe-l(f)g march 2004 29 mobile-ddr sdram functional truth table abbreviations : h=high level, l=low level, x=don t care note : 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state ; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around and write recovery requirements. 4. nop to bank precharging or in idle sate. may precharge bank indicated by ba. 5. illegal if any bank is not idle. 6. refer to "3.3.10 read with auto precharge" for detailed information. 7. refer to "3.3.11 write with auto precharge" for detailed information. 8. cke low to high transition will re-enable ck, ck and other inputs asynchronously. a minimum setup time must be satisfied before issuing any command other than exit. 9. power-down and self-refresh can be entered only from all bank idle state. illegal = device operation and/or data integrity are not guaranteed. current state cke n-1 cke n cs ras cas we add action self- refreshing *8 l h h x x x x exit self-refresh lhlhhhxexit self-refresh lhlhhlxillegal lhlhlxxillegal l h l l x x x illegal l l x x x x x noperation(maintain self-refresh) power down l h x x x x x exit power down(idle after tpdex) l l x x x x x noperation(maintain power down) all banks idle *9 h h x x x x x refer to function true table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state=power down any state other than listed above h h x x x x x refer to function truth table
k4x56163pe-l(f)g march 2004 30 mobile-ddr sdram dc operating conditions & specifications dc operating conditions absolute maximum ratings note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommend operation condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 2.7 v voltage on v dd supply relative to v ss v dd -0.5 ~ 2.7 v voltage on v ddq supply relative to v ss v ddq -0.5 ~ 2.7 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma table 10. absolute maximum ratings recommended operating conditions (voltage referenced to vss=0v, ta= -25 c to 85 c) notes : 1. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. parameter symbol min max unit note supply voltage(for device with a nominal vdd of 1.8v) vdd 1.7 1.95 i/o supply voltage vddq 1.7 1.95 v input logic high voltage vih(dc) 0.7 x vddq vddq+0.3 v 1 input logic low voltage vil(dc) -0.3 0.3 x vddq v 1 output logic high voltage voh(dc) 0.9 x vddq - v ioh = -0.1ma output logic low voltage vol(dc) - 0.1 x vddq v iol = 0.1ma input leakage current ii -2 2 ua output leakage current ioz -5 5 ua
k4x56163pe-l(f)g march 2004 31 mobile-ddr sdram recommended operating conditions (voltage referenced to v ss = 0v, temp = -25 to 85 c) notes: 1. idd specifications are tested after the device is properly intialized. 2. input slew rate is 1v/ns. parameter symbol test condition ddr200 ddr133 unit operating current (one bank active) i cc0 t rc = t rcmin ; t ck = t ckmin ; cke is high; cs is high between valid commands; address inputs are switching; data bus inputs are sta- ble 30 30 ma precharge standby current in power-down mode i cc2 p all banks idle, cke is low; cs is high, t ck = t ckmin ; address and control inputs are switching; data bus inputs are stable 0.3 ma i cc2 ps all banks idle, cke is low; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 0.3 precharge standby current in non power-down mode i cc2 n all banks idle, cke is high; cs is high, t ck = t ckmin ;address and control inputs are switching; data bus inputs are stable 8 8 ma i cc2 ns all banks idle, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 4 4 active standby current in power-down mode i cc3 p one bank active, cke is low; cs is high, t ck = t ckmin ;address and control inputs are switching; data bus inputs are stable 3 ma i cc3 ps one bank active, cke is low; cs is high, ck = low, ck = high;address and control inputs are switching; data bus inputs are stable 1 active standby current in non power-down mode (one bank active) i cc3 n one bank active, cke is high; cs is high, t ck = t ckmin ;address and control inputs are switching; data bus inputs are stable 10 10 ma i cc3 ns one bank active, cke is high; cs is high, ck = low, ck = high; address and control inputs are switching; data bus inputs are stable 6 6 ma operating current (burst mode) i cc 4r one bank active; bl = 4; cl = 3; t ck = t ckmin ; continuous read bursts; i out = 0 ma address inputs are switching; 50% data change each burst transfer 65 55 ma i cc 4w one bank active; bl = 4; t ck = t ckmin ; continuous write bursts;address inputs are switching; 50% data change each burst transfer 65 55 ma refresh current i cc 5 t rc = t rfcmin ; t ck = t ckmin ; burst refresh; cke is high;address and control inputs are switching; data bus inputs are stable 80 80 ma self refresh current i cc 6 cke is low; t ck = t ckmin ; extended mode register set to all 0?s; address and control inputs are stable; data bus inputs are stable tcsr range max 40 max 85 c full array 150 400 ua 1/2 array 125 300 1/4 array 115 250 dc characteristics
k4x56163pe-l(f)g march 2004 32 mobile-ddr sdram ac operating conditions & timming specification note : 1. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. parameter/condition symbol min max unit note input high (logic 1) voltage, all inputs vih(ac) 0.8 x vddq vddq+0.3 v 1 input low (logic 0) voltage, all inputs vil(ac) -0.3 0.2 x vddq v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.4 x vddq 0.6 x vddq v 2 3. definitions for idd: low is defined as v in 0.1 * v ddq ; high is defined as v in 0.9 * v ddq ; stable is defined as inputs stable at a high or low level; switching is defined as: - address and command: inputs changing between high and low once per two clock cycles - data bus inputs: dq changing between high and low once per clock cycle; dm and dqs are stable.
k4x56163pe-l(f)g march 2004 33 mobile-ddr sdram ac timming parameters & specifications parameter symbol ddr200 ddr133 unit note min max min max clock cycle time cl=3.0 tck 10 15 ns 1 row cycle time trc 80 90 ns row active time tras 50 60 ns ras to cas delay trcd 30 30 ns row precharge time trp 30 30 ns row active to row active delay trrd 15 15 ns write recovery time twr 15 30 ns last data in to active delay tdal twr+trp twr+trp - 2 last data in to read command tcdlr 1 1 tck col. address to col. address delay tccd 1 1 tck clock high level width tch 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 tck output data access time from ck/ck cl=3.0 tsac 2.0 7.0 2.0 7.0 ns 3 data strobe edge to ouput data edge tdqsq 0.7 0.9 ns 1 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 ns 4 dqs-in hold time twpreh 0.25 0.25 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 tck address and control input setup time tis 1.5 2.0 ns 1 address and control input hold time tih 1.5 2.0 ns 1 dq & dm setup time to dqs tds 1.1 1.5 ns 5,6 dq & dm hold time to dqs tdh 1.1 1.5 ns 5,6 dq & dm input pulse width tdipw 2.2 3.0 ns dqs write postamble time twpst 0.4 0.6 0.4 0.6 tck refresh interval time 256mb tref 7.8 7.8 us mode register set cycle time tmrd 2 2 tck power down exit time tpdex 1*tck +tis 1*tck +tis ns auto refresh cycle time tarfc 80 80 ns exit self refresh to active command tsrfx 120 120 ns data hold from dqs to earliest dq edge tqh thpmin - 1.0ns thpmin - 1.0ns ns clock half period thp tclmin or tchmin tclmin or tchmin ns
k4x56163pe-l(f)g march 2004 34 mobile-ddr sdram 1. input setup/hold slew rate derating this derating tabl e is used to increase t is /t ih in the case where the input slew rate is below 1.0v/ns. 2. minimum 3clk of tdal(= twr + trp) is required be cause it need minimum 2clk for twr and minimum 1clk for trp. 3. tsac(min) value is measured at the hi gh vdd(1.95v) and cold temperature(-25 c). tsac(max) value is measured at the low vdd(1.7v) and hot temperature(85 c). tsac is measured in the device with half driver strength and under the ac outpu t load condition (fig.2 in next page). 4. the specific requirement is that dq s be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were prev iously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 5. i/o setup/hold slew rate derating this derating table is used to increase t ds /t dh in the case where the i/o sl ew rate is below 1.0v/ns. 6. i/o delta rise/fall ra te(1/slew-rate) derating this derating table is used to increase tds/tdh in the case where the dq and dqs slew rates differ. the delta rise/fall rat e is calculated as 1/slewrate1-1/slew rate2. for example, if slew rate 1 = 1.0v/n s and slew rate 2 =0.8v/ns, then the delta r ise/fall rate =-0.25ns/v. input setup/hold slew rate ? tis ? tih (v/ns) (ps) (ps) 1.0 0 0 0.8 +50 +50 0.6 +100 +100 i/o setup/hold slew rate ? tds ? tdh (v/ns) (ps) (ps) 1.0 0 0 0.8 +75 +75 0.6 +150 +150 delta rise/fall rate ? tds ? tdh (ns/v) (ps) (ps) 000 0.25 +50 +50 0.5 +100 +100
k4x56163pe-l(f)g march 2004 35 mobile-ddr sdram input/output capacitance (v dd =1.8v, v ddq =1.8v, t a = 25 c , f=1mhz) parameter symbol min max unit input capacitance (a0 ~ a12, ba0 ~ ba1, cke, cs , ras ,cas , we ) cin1 1.5 3.0 pf input capacitance( ck, ck ) cin2 1.5 3.0 pf data & dqs input/output capacitance cout 3.0 5.0 pf input capacitance(dm) cin3 3.0 5.0 pf 1.8v 13.9k ? 10.6k ? output 30pf v oh (dc) = 0.9 x vddq, i oh = -0.1ma v ol (dc) = 0.1 x vddq, i ol = 0.1ma vtt=0.5 x v ddq 50 ? output 30pf z0=50 ? (fig. 2) ac output load circuit (fig. 1) dc output load circuit ac operating test conditions (v dd = 1.7v - 1.95v, t a = -25 to 85 c) parameter value unit ac input levels (vih/vil) 0.8 x vddq / 0.2 x vddq v input timing measurement reference level 0.5 x vddq v input signal minimum slew rate 1.0 v/ns output timing measurement reference level 0.5 x vddq v output load condition see fig. 2
k4x56163pe-l(f)g march 2004 36 mobile-ddr sdram 0123456789101112131415 cke cs ras cas a10/ap addr dqs we (a0~an) dq : don?t care ck ck basic timing (setup, hold and access time @bl=4, cl=3) high baa dm command active t rpre read write baa bab ra ra ca cb db0 db1 db2 db3 qa0 qa1 qa2 qa3 t dqsq t sac t hzq hi-z t wpres t dqss t dsc t dqsh t dqsl t wpst t rps hi-z t ds t dh t ck t ch t cl t ck t ch t cl t is t ih ba0, ba1
k4x56163pe-l(f)g march 2004 37 mobile-ddr sdram 0123456789101112131415 cke cs ras cas ba0,ba1 a10/ap addr dqs we (a0~an) dq : don?t care ck ck multi bank interleavi ng read (@bl=4, cl=3) high baa dm command qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 active t rrd t ccd bab baa bab ra ra rb ca cb active read read t rcd rb
k4x56163pe-l(f)g march 2004 38 mobile-ddr sdram 0123456789101112131415 cke cs ras cas ba0,ba1 a10/ap addr dqs we (a0~an) dq : don?t care ck ck multi bank interleaving write (@bl=4) high baa dm command da0 da1 da2 da3 db0 db1 db2 db3 active t rrd t ccd bab baa bab ra ra ra rb ca cb active write write t rcd
k4x56163pe-l(f)g march 2004 39 mobile-ddr sdram 012345678910 cke cs ras cas a10/ap addr dq dqs ba0,ba1 (a0~an) dm : don?t care ck ck read with auto precharge (@bl=8) high baa qa0 qa1 qa2 qa4 qa5 qa6 we command read qa7 qa3 active bab ra ca cb (cl=3) (cl=3) auto precharge start t rp note 1 note: the row active command of the precharge bank can be issued after trp from this point the new read/write command of another activated bank can be issued from this point at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal.
k4x56163pe-l(f)g march 2004 40 mobile-ddr sdram 0123456789101112131415 auto precharge start cke cs ras cas ba0,ba1 a10/ap addr dqs we (a0~an) dq : don?t care ck ck write with auto precharge (@bl=8) high baa bab ra ca cb dm command da0 da1 da2 da3 da4 da5 da6 da7 write active note 1 t wr t rp note: 1. the row active command of the precharge bank can be issued after trp from this point the new read/write command of another activated bank can be issued from this point at burst read/write with auto precharge, cas interrupt of the same/another bank is illegal.
k4x56163pe-l(f)g march 2004 41 mobile-ddr sdram 012345678910 cke cs ras cas a10/ap addr dq dqs ba0,ba1 (a0~an) dm : don?t care ck ck write followed by precharge (@bl=4) high da0 da1 da2 da3 we command write baa ca pre charge t wr baa
k4x56163pe-l(f)g march 2004 42 mobile-ddr sdram 012345678910 cke cs ras cas a10/ap addr dq dqs ba0,ba1 (a0~an) dm : don?t care ck ck write interrupted by precharge & dm (@bl=8) high baa da0 da1 da2 da3 da4 da6 da7 we command write da5 t wr bab bac baa ca cb cc db0 db1 dc0 dc2 dc3 dc1 t ccd pre charge write write
k4x56163pe-l(f)g march 2004 43 mobile-ddr sdram 012345678910 cke cs ras cas a10/ap addr dq dqs ba0,ba1 (a0~an) dm : don?t care ck ck write interrupted by a read (@bl=8, cl=3) high da0 da1 da2 da3 da4 da5 we command write bab ca cb qb0 qb1 qb2 qb3 read t cdlr masked by dm baa
k4x56163pe-l(f)g march 2004 44 mobile-ddr sdram 012345678910 cke cs ras cas a10/ap addr dq(cl=3) dqs(cl=3) ba0,ba1 (a0~an) dm : don?t care ck ck read interrupted by precharge (@bl=8) high qa0 qa1 qa2 qa3 qa4 we command read baa qa5 pre baa ca charge 2 t ck valid 4
k4x56163pe-l(f)g march 2004 45 mobile-ddr sdram 012345678910 cke cs ras cas a10/ap addr dq dqs ba0,ba1 (a0~an) dm : don?t care ck ck read interrupted by a write & burst stop (@bl=8, cl=3) high qa0 qa1 qb0 qb1 qb2 qb4 qb5 qb6 we command read baa qb7 qb3 burst bab ca cb write stop
k4x56163pe-l(f)g march 2004 46 mobile-ddr sdram 012345678910 cke cs ras cas a10/ap addr dq dqs ba0,ba1 (a0~an) dm : don?t care ck ck read interrupted by a read (@bl=8, cl=3) high baa qa0 qa1 qb0 qb1 qb2 qb4 qb5 qb6 we command read bab ca cb qb7 qb3 t ccd read
k4x56163pe-l(f)g march 2004 47 mobile-ddr sdram 012345678910 cke cs ras cas a10/ap addr dq dqs ba0,ba1 (a0~an) dm : don?t care ck ck dm function (@bl=8) only for write high baa ca da0 da1 da2 da3 da5 da6 da7 we command write da4
k4x56163pe-l(f)g march 2004 48 mobile-ddr sdram 012345678910111213141516171819 t ck t rp 4 clock high-z high-z precharge command all bank mode resister set command any command cke cs ras cas ba0,ba1 a10/ap addr dq dm we note : power & clock must be stable for 200us before precharge all bankes (a0~an) dqs : don?t care ck ck mode register set address key

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